Integrated circuits, especially logic circuits are often tested using scan chain methodology, wherein, test patterns are loaded into a set of scan-in latches, clocked through the combinational logic to be tested and the result pattern captured by scan-out latches for analysis. This testing has been traditionally performed at tester frequencies of about 30 to 100 MHz. However, with the advent of higher functional frequency integrated circuits, for example in about the 1 to 5 GHz range, circuits have been found to pass at tester frequency but fail at functional frequency. Therefore, there is a need for a method and circuit for testing integrated circuits at functional frequency.